1. Field of the Invention
This invention relates to a semiconductor integrated circuit including a sense circuit capable of handling an input signal whose amplitude is small.
2. Description of the Related Art
An input buffer circuit capable of handling a signal whose amplitude is small, has been required as one technique (disclosed in, for example, a technical publication I ("Nikkei Electronics", no. 556, pp. 133.about.141, Jun., 8, 1992)) for realizing a semiconductor integrated circuit activated at higher speed. An example in which a semiconductor integrated circuit having an input buffer circuit incorporated therein and called a "GTL" (Gunning Transceiver Logic) as one example, is constructed, has been disclosed on page 136 of the technical publication I in particular. FIG. 13 is a circuit diagram showing the "GTL" input buffer circuit. The input buffer circuit comprises a terminal (input terminal) IN to which an input signal whose amplitude is small is supplied, a sense circuit (sense amplifier) 20 composed of P-channel MOS (Metal Oxide Semiconductor) field effect transistors (also hereinafter called "P-MOSs") 21, 22 and 23 and N-channel MOS field effect transistors (also hereinafter called "N-MOSs") 24 and 25, a reference voltage supply terminal REF and an output terminal OUT. In the input buffer circuit, a signal N21 of a low or high level is outputted depending on whether a voltage inputted to the input terminal IN is higher or lower than a voltage at the reference voltage supply terminal REF. The low or high level signal N21 is transmitted to an output terminal OUT through both an inverter circuit INV composed of a P-MOS 26 and N-MOSs 27 and 28, and inverters 29 and 30. Incidentally, the N-MOS 27 in the inverter circuit INV is of a transistor for taking countermeasures against hot carriers. Further, the reference voltage is determined as 0.8 V and the input voltage is determined so as to range from about 0 V to 1.2 V in accordance with the GTL standards.
A test for measuring a current flowing from a power source to GND in a state in which a predetermined quiescent test signal has been applied to a terminal of a semiconductor integrated circuit, a so-called method of measuring a current that flows upon deactivation of the semiconductor integrated circuit, is carried out as an on-shipment test when the semiconductor integrated circuit is shipped. This is carried out because the result of measurement can be used as one criteria for judging whether damaged or broken spots exist in transistors employed in the semiconductor integrated circuit. Even in the case of a semiconductor integrated circuit provided with the input buffer circuit shown in FIG. 13 as an input portion, a current that flows upon deactivation of the semiconductor integrated circuit, is measured for the purpose of testing a principal portion of the semiconductor integrated circuit upon shipment thereof. Since, however, the amplitude of an input signal is smaller than that of a power source voltage in the input buffer circuit, the P-MOSs 21, 22 and 23 and the N-MOSs 24 and 25 are kept ON at all times. Therefore, a current i21 (see FIG. 13) always flows in a sense circuit 20 upon measuring the current that flows when the semiconductor integrated circuit is deactivated. When the current that flows upon deactivation of the semiconductor integrated circuit, is measured, this current i21 makes it difficult to make a decision as to whether damaged or broken spots exist in the transistors employed in the semiconductor integrated circuit.
In order to avoid the above problem, it is considered that the consumed current i21 is prevented from flowing on condition that the input voltage at the input terminal IN is V.sub.DD and the P-MOS 21 is in an OFF state. Since, however, the P-MOS 22 and the N-MOS 24 are respectively brought into an OFF state at this time, the signal N21 is brought into a high impedance state (floating state). Therefore, a current flows which is consumed by the inverter circuit INV composed of the P-MOS 26 and the N-MOSs 27 and 28. Upon measurement of the on-deactivation current, the current consumed by the inverter circuit INV makes it difficult to judge whether the damaged or broken spots exist in the transistors employed in the semiconductor integrated circuit.